FIG. 1 is a block diagram of an exemplary general related art network apparatus used for line switching. Referring to FIG. 1, a network apparatus 1 includes a plurality of input interface units 2, working and protection line switching units (STS-SWs: synchronous transport signal switches) 3W and 3P, a plurality of output interface units 4, and a central processing unit (CPU) 5.
The input interface units 2 receive optical transmission data in a format such as OC (optical carrier)-12/48/192/768 transmitted from another SONET network apparatus (not illustrated), and after conversion into electrical signals, transfer the transmission data to the line switching units 3W and 3P. The output interface units 4 convert transmission data transferred from the line switching units 3W and 3P into optical signals in a format such as OC-12/48/192/768, and transmit the transmission data to another SONET network apparatus (not illustrated).
In the line switching units 3W and 3P, data input from each channel (corresponding to STS-1, which is the smallest unit) of the input interface units 2 is subjected to cross-connection processing (switching processing) or the like which controls which channel of which interface unit 4 the data is to be output to, on the basis of the state of transmission lines and software-set information from the CPU 5, and is transferred to a predetermined channel of the interface units 4.
The line switching units 3W and 3P are respectively a working unit and a protection unit constituting a redundant system configuration (dual configuration). When a failure occurs in the working line switching unit 3W, the CPU 5 is notified of the occurrence of the failure. The CPU 5, receiving the failure occurrence notification, controls the output interface units 4 such that transmission signals to be selected are changed from those of the working line switching unit 3W over to those of the protection line switching unit 3P. The CPU 5 performs line setting for the line switching units 3W and 3P, line setting for the interface units 2 and 4, the monitoring of line states, and line changeover control. Note that the CPU 5 is also configured as a dual system in preparation for failures.
Recent rapid progress in the miniaturization of devices, such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs), has increasingly resulted in malfunctions due to bit inversion (soft errors) in memory devices caused by cosmic rays, such as a particles or neutrons. Hence, it has become important for an apparatus to have a configuration which prevents malfunctions caused by memory errors including such soft errors.
FIG. 2 is a detailed configuration diagram of line switching units of the related art network apparatus. Referring to FIG. 2, the working line switching unit 3W and the protection line switching unit 3P have the same configuration, and each include a control signal generation unit 31 and a main signal processing unit 32. The control signal generation unit 31 includes a memory 311, a control signal processing unit 312, and a memory error detection processing unit 313. The main signal processing unit 32 includes a cross-connection processing unit 321, which includes a buffer 322. The interface unit 4 is provided with a selector 41.
In the control signal generation unit 31, the memory 311 stores switching control information set by the CPU 5 and intermediate information, and the control signal processing unit 312 generates a line switching control signal on the basis of the information stored in the memory 311 by the CPU 5. When these kinds of information are stored in the memory 311, information (parity information) for error detection is added to and stored with the kinds of information. The memory error detection processing unit 313, when reading data, checks the read data and notifies the CPU 5 of error information upon detection of a memory error.
The information described above is stored in the buffer 322 from a line switching control signal received from the control signal processing unit 312 of the control signal generation unit 31. The main signal processing unit 32 performs line switching control based on this information, and outputs a main signal that has been subjected to line switching to the output interface units 4. The selector 41 of the interface unit 4 normally selects the output from the main signal processing unit 32 of the working line switching unit 3W, and transfers the output to a subsequent processing circuit.
The CPU 5, upon receipt of an error notification from the control signal generation unit 31 of the working line switching unit 3W, changes the output from the working line switching unit 3W over to the output from the protection line switching unit 3P, by controlling the selector 41 of the interface unit 4. Note that when the memory error is a soft error due to cosmic rays such as a particles or neutrons, recovery from the error is achieved by resetting the data of the memory 311 of the working line switching unit 3W. However, since it is difficult to discriminate such soft errors from permanent errors, changeover to the output from the protection line switching unit 3P is performed in either case. When recovery from the error of the working line switching unit 3W is achieved later under the monitoring of the CPU 5, whether the output of the working line switching unit 3W is selected at this time or at the occurrence of a new failure depends on the applications being used.
Related techniques are disclosed in Japanese Unexamined Patent Application Publication No. 2007-188428 and Japanese Patent No. 4003620.